Diffused MOS (DMOS) devices had been available in the prior art and are described, for example, in T. J. Rodgers, et al., "An Experimental and Theoretical Analysis of Double Diffused DMOS Transistors," IEEE Journal of Solid State Circuits, October 1975, pages 322-331. A cross-sectional view of a typical prior art DMOS device is shown in FIG. 1. It consists of a P-type silicon substrate 2 with an N-type epitaxial layer 4 deposited thereon and into which diffusions will be driven. Two diffusions are needed, a first P-type diffusion 8 defines a channel length of about 1 micron and a P-type diffusion 6 serves as the device isolation region. A second N-type diffusion is provided for the source 10 and drain 12 of the DMOS device. The effective channel region 14 lies between the region 16 of the N-type epitaxial layer 4 and the source 10. The device is completed by depositing a thin oxide layer 19 over the channel region 14. A thick oxide layer 18 is deposited over the rest of the device, with a window over the source region 10 to enable its contact with the source contact 20 and a window over the drain region 12 to enable the drain contact 24 to electrically contact the drain 12. A metal or polysilicon gate layer 22 is then deposited over the thin oxide region 19 to complete the device.
The principal advantage of the prior art DMOS device shown in FIG. 1 is its ability to define the channel length 14 of about 1 micron by means of hot processing steps rather than photolithographic techniques. However, this structure and fabrication process is not suited for a large scale integrated circuitry for several reasons. First, it requires an epitaxial layer 4 whose thickness of about 2 to 3 microns introduces variations which detract from the yield because of nucleation phenomena. Secondly, the isolation diffusion 6 tends to consume a great deal of silicon wafer area. Thirdly, an extra mask is required in order to open the window for the electrode 24 above the drain region 12, after the P-type diffusion 14 has taken place.
To overcome some of these drawbacks, modified DMOS structures have been introduced in the prior art, such as shown in FIG. 2. Here, a structure is obtained using a simpler processing sequence which eliminates the N-type epitaxial layer 4 of FIG. 1 and employs instead a single P-type substrate 26. Otherwise, the structure shown in FIG. 2 is the same as that shown in FIG. 1 and the reference symbols for the two figures are identical.
In the above-referenced publication by Rodgers, et al., it is analytically shown that in order to have the device of FIG. 2 approach the same drain-to-source current versus drain-to-source voltage characteristics of the device in FIG. 1, the following inequality must be satisfied: EQU .DELTA.V.sub.T =(V.sub.TE -V.sub.TD)&gt;1/2E.sub.C L.sub.D.
V.sub.TE is the threshold voltage corresponding to the heavily doped enhancement portion 14 of the channel, designated L.sub.E. V.sub.TD corresponds to the lightly doped or depletion portion of the channel 16, designated L.sub.D. E.sub.C is the critical electric field of 2.times.10.sup.4 volts per centimeter where electron velocity saturation begins to set in.
In order to satisfy the inequality, the following steps could be taken. One could make L.sub.D short, on the order of 1 micron for .DELTA.V.sub.T of 2 volts. However this is not a practical option since it requires tight tolerances on mask dimensions and their alignment which is the type of problem which DMOS is supposed to avoid.
Alternately, one could make V.sub.TD as negative as possible by using a high resistivity substrate, as for example the 100 ohm-centimeter substrate described in K. Ohta, et al., "A High Speed Logic LSI Using Difusion Self-Aligned Enhancement Depletion MOS IC," IEEE Journal of Solid State Circuits, October 1975, pages 314,-322. However this option creates the problems of surface leakage and punchthrough.